05636174 is referenced by 97 patents and cites 9 patents.

A memory 200 comprising a plurality of rows and columns of memory cells, each column of cells associated with a conductive bitline 301. Memory 200 further includes precharge circuitry 204, 206 for precharging a selected one of the bitlines in response to a received control bit.

Title
Fast cycle time-low latency dynamic random access memories and systems and methods using the same
Application Number
8/584565
Publication Number
5636174
Application Date
January 11, 1996
Publication Date
June 3, 1997
Inventor
G R Mohan Rao
Dallas
TX, US
Agent
Winstead Sechrest & Minick
Assignee
Cirrus Logic
CA, US
IPC
G11C 8/00
G11C 7/02
G11C 7/00
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