05625837 is referenced by 120 patents and cites 14 patents.

A processor architecture is described which operates with improved computational efficiency using instruction fetching functions that are decoupled from instruction execution functions by a dynamic register file. The instruction fetching function operates in free-running mode which does not stop if a fetched instruction cannot be executed due to data being unavailable or due to other instruction dependencies. Branch instructions are taken in a predicted direction and the results of execution of all instructions are provisionally stored pending validation or invalidation on the basis of the dependencies becoming available later. For branches of executed instructions that are later invalidated, the results of the executed instructions are flushed from provisional storage and the initial instruction which previously executed at the beginning of a branch on predicted dependencies is re-executed on the actual data that subsequently became available, and all subsequent instructions in such branch are also re-executed on the basis of dependencies actually available from execution of previous instructions in such branch.

Title
Processor architecture having out-of-order execution, speculative branching, and giving priority to instructions which affect a condition code
Application Number
451403
Publication Number
5625837
Application Date
June 6, 1995
Publication Date
April 29, 1997
Inventor
Bruce D Lightner
San Diego
CA, US
John E Spracklen
San Diego
CA, US
Gary A Gibson
Carlsbad
CA, US
Merle A Schultz
Escondido
CA, US
Valeri Popescu
San Diego
CA, US
Agent
Townsend and Townsend and Crew
Assignee
Hyundai Electronics America
CA, US
IPC
G06F 9/30
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