05623628 is referenced by 137 patents and cites 4 patents.

A computer system, and a method performed by it, having a mechanism for ensuring consistency of data among various level(s) of caching in a multi-level hierarchical memory system. The cache consistency mechanism includes an external bus request queue which and associated mechanism, which cooperate to monitor and control the issuance of data requests, such as read requests and write requests, onto an external bus. The computer system includes one or more CPUs each having this consistency mechanism.

Title
Computer system and method for maintaining memory consistency in a pipelined, non-blocking caching bus request queue
Application Number
8/205040
Publication Number
5623628
Application Date
March 2, 1994
Publication Date
April 22, 1997
Inventor
Glenn J Hinton
Portland
OR, US
Nitin V Sarangdhar
Beaverton
OR, US
Michael W Rhodehamel
Beaverton
OR, US
James M Brayton
Beaverton
OR, US
Agent
Blakely Sokoloff Taylor & Zafman
Assignee
Intel Corporation
CA, US
IPC
G06F 12/00
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