05610426 is referenced by 27 patents and cites 11 patents.

A protective circuit that can maintain effectiveness when excess voltages of both polarities are applied is placed between the input terminal of an internal CMOS inverter and an input pad. The protective circuit includes a protective resistor, a P-channel MOSFET and an N-channel MOSFET. The N-channel MOSFET is placed between a connecting line and a ground terminal with the gate terminal of the MOSFET connected to the connecting line. The P-channel MOSFET is placed between the connecting line and the ground terminal with the gate terminal of the MOSFET connected to the connecting line. The P-channel MOSFET releases excess negative voltage from the outside using ON-state current and the N-channel MOSFET releases excess positive voltage from the outside using ON-state current.

Title
Semiconductor integrated circuit device having excellent dual polarity overvoltage protection characteristics
Application Number
8/505819
Publication Number
5610426
Application Date
July 21, 1995
Publication Date
March 11, 1997
Inventor
Takeshi Enya
Nagoya
JP
Kazuhiro Tsuruta
Toyoake
JP
Akiyoshi Asai
Aichi-gun
JP
Agent
Cushman Darby & Cushman Ip Group of Pillsbury Maidson & Sutro
Assignee
Nippondenso
JP
IPC
H01L 23/62
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