05606686 is referenced by 41 patents and cites 7 patents.

A main memory shared by plural processing units in a parallel computer system is composed of plural partial main memories. A directory for each data line of the main memory is generated after the data line has been cached in one of the processing units. The directory is held in one of the partial main memories in place of the data line. The directory indicates a processing unit which has cached the data line. A status bit C provided for the data line is set. If a subsequent read request is given to the data line, the status C bit is checked and the directory is used to identify a processing unit that has cached the data line. The request is transferred to the identified processing unit, and the data line is transferred from that processing unit to the processing unit that has issued the request. If a processing unit that has cached the data line has replaced the data line, it is checked if there is a processing unit that has cached the data line. If there is none, the data line is written back into the one partial main memory. If there is, the data line is not written back. Another status bit RO is also used for each data line. It indicates if the data line is read only. If a data line is read only, generation of the directory and storing it in the partial main memory is prohibited.

Title
Access control method for a shared main memory in a multiprocessor based upon a directory held at a storage location of data in the memory after reading data to a processor
Application Number
8/328759
Publication Number
5606686
Application Date
October 24, 1994
Publication Date
February 25, 1997
Inventor
Katsuyoshi Kitai
Kokubunji
JP
Hiroaki Fujii
Hadano
JP
Naonobu Sukegawa
Kokubunji
JP
Toshiaki Tarui
Kokubunji
JP
Agent
Antonelli Terry Stout & Kraus
Assignee
Hitachi
JP
IPC
G06F 12/08
View Original Source