05603005 is referenced by 61 patents and cites 44 patents.

A method and apparatus for identifying obsolete data within cache memory in a multiprocessor architecture. This is accomplished while still providing the advantages of having cache resources dedicated to individual instruction processors as well as shared intermediate level cache modules. The technique provides the band pass and attendant performance advantages of an essentially point-to-point architecture without all of the added hardware of a centralized master system storage controller. Further, unlike a strictly point-to-point architecture, the present invention is readily expandable to service a large number of multiprocessors without burdening each of the multiprocessors with the corresponding increase in interface and connection costs of a strictly point-to-point architecture. This simplifies the design of the multiprocessor elements and also allows a system to be expanded to include more or less multiprocessors by simply including a modified XBAR interface. In a strictly point-to-point architecture, the multiprocessors may have to be modified to expanding a system because the interfacing circuitry associated therewith is contained therein. The present invention further has a means for increasing the performance of the XBAR interface by providing an anticipatory acknowledge signal back to a requesting multiprocessor.

Title
Cache coherency scheme for XBAR storage structure with delayed invalidates until associated write request is executed
Application Number
8/364760
Publication Number
5603005
Application Date
December 27, 1994
Publication Date
February 11, 1997
Inventor
Michael Haupt
Roseville
MN, US
Mitchell Bauman
Circle Pines
MN, US
Agent
Nawrocki Rooney & Sivertson P A
Assignee
Unisys Corporation
PA, US
IPC
G06F 13/00
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