05603001 is referenced by 303 patents and cites 7 patents.

A NAND bus interface independently receives 16 ready/busy signals from 16 flash EEPROM chips and thereby separately manages the operating states of these flash EEPROMs. Once a flash EEPROM as a write access target is set in a ready state, a write access to this write access target flash EEPROM is started without waiting for completion of the operations of all the flash EEPROMs. Each flash EEPROM is of a command control type capable of automatically executing a write operation. This allows parallel processing of the flash EEPROMs, i.e., a write access to a given EEPROM can be performed while a data write to another flash EEPROM is being executed. An ECC calculating circuit calculates a data string transferred in units of 256 bytes from a data buffer by a processor, and generates an ECC corresponding to that data string. The 256-byte data string is added with the generated ECC and transferred to a data register of a flash EEPROM. Even if abnormal cells are produced at the same bit position in a plurality of pages of a flash EEPROM, only one abnormal cell is contained in a data string as an object of the ECC calculation. This makes it possible to perform error detection and correction by a common simple ECC calculation without using any complicated ECC arithmetic expression with a high data recovery capability.

Title
Semiconductor disk system having a plurality of flash memories
Application Number
8/435854
Publication Number
5603001
Application Date
May 5, 1995
Publication Date
February 11, 1997
Inventor
Takashi Inagaki
Tokyo
JP
Yasunori Maki
Tokyo
JP
Hiroshi Sukegawa
Tokyo
JP
Agent
Finnegan Henderson Farabow Garrett & Dunner L
Assignee
Kabushiki Kaisha Toshiba
JP
IPC
G06F 13/00
G06F 12/00
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