05600606 is referenced by 26 patents and cites 13 patents.

A method of operating a memory device including a plurality of data/address input/output terminals, an array of memory cells and circuitry for accessing selected ones of the memory cells in response to received address bits. At least one row address bit and at least one column address bit are substantially simultaneously input during an address cycle, at least one of the address bits being input through a selected one of the multiplexed terminals. The memory cells addressed by the row and column bits are then accessed through selected ones of the multiplexed terminals during a data access cycle.

Title
Low pin count - wide memory devices using non-multiplexed addressing and systems and methods using the same
Application Number
521867
Publication Number
5600606
Application Date
March 7, 1996
Publication Date
February 4, 1997
Inventor
G R Mohan Rao
Dallas
TX, US
Agent
Winstead Sechrest & Minick P C
Assignee
Cirrus Logic
CA, US
IPC
G11C 8/00
G11C 7/00
View Original Source