05598546 is referenced by 230 patents and cites 15 patents.

A dual-instruction-set processor processes instructions from two or more instruction sets. The processor has several pipelines for processing different types of operations--Memory, ALU, and Branch operations. Instructions are decoded by RISC and CISC instruction decoders which generate control words for the pipelines. The control words are encoded by the operation to be performed by the pipelines, which can overlap for the instruction sets. A different format for the control word is used for each pipeline, but the format is the same for all instruction sets. Once the control words are generated and sent to the pipelines, an indication of the instruction set is no longer needed. Thus instructions from several instruction sets may be freely mixed in the pipelines, and there is no need to flush the pipelines when the instruction set is switched. Register operands are first converted to their RISC equivalents by the instruction decoders so that bypass and interlock logic may detect dependencies between instructions from any instruction set. Pipeline valid bits encode the order that instructions were in, allowing dependencies to exist within a group of instructions at the same stage in the pipelines. A dispatcher can decode and dispatch up to three instructions in a single clock cycle, although the third instruction dispatched can only be a simple branch. Compound instructions may require more than one pipeline for processing, and two or more control words are generated for these complex instructions, with one control word sent to each pipeline.

Dual-architecture super-scalar pipeline
Application Number
Publication Number
Application Date
August 31, 1994
Publication Date
January 28, 1997
James S Blomgren
San Jose
Stuart T Auvinen
Exponential Technology
G06F 9/30
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