A system is disclosed for synthesizing field programmable gate array (FPGA) implementations from high level circuit descriptions. A designer may describe circuits using a textual language or a graphics tool. The system will compile such circuit descriptions into technology mapped descriptions for use with FPGA's.
The system will support both random logic circuits and data path circuits. The system uses advanced optimization techniques to produce efficient FPGA implementations. Thus, the system produces high quality results while providing users with a high level of abstraction in design, and thus frees the user from architectural details of the target FPGA.