05585308 is referenced by 59 patents and cites 12 patents.

A method of forming an integrated circuit wherein a planarization step is been performed before the primary metal deposition step, but after deposition of the adhesion and barrier layers. Thus the adhesion and barrier layers are present on the sidewalls of contact holes, but do not underlie the whole extent of the primary metallization.

Title
Method for improved pre-metal planarization
Application Number
172487
Publication Number
5585308
Application Date
March 29, 1995
Publication Date
December 17, 1996
Inventor
John C Sardella
Highland Village
TX, US
Agent
Lisa K Jorgenson
Robert Groover
Theodore E Galanthay
Assignee
SGS Thomson Microelectronics
TX, US
IPC
H01L 21/28
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