05581767 is referenced by 187 patents and cites 8 patents.

The processor section comprises a matrix-line layout of processor units; each processor unit combined with adjacent processor units in row and column direction by means of IPC buses, which are two-way buses. The control/memory section comprises arrays of control/memory units corresponding one-to-one to the processor units; each control/memory unit entering instructions and data simultaneously to the corresponding units in the processor section via optical channels to carry out arithmetic operations. By providing grid-like buses on the control/memory-unit arrays, and transferring instructions and data on the buses and sending them to the processor unit corresponding one-to-one to the control/memory unit to which data are transferred via optical channels, the transfer of instructions and data is carried out efficiently between processor units beyond the third closest ones.

Title
Bus structure for multiprocessor system having separated processor section and control/memory section
Application Number
78758
Publication Number
5581767
Application Date
November 28, 1994
Publication Date
December 3, 1996
Inventor
Danny Chin
Princeton Junction
NJ, US
Donald J Sauer
Allentown
NJ, US
Kazuo Katsuki
Hyogo
JP
Agent
Ratner & Prestia
Assignee
Nippon Sheet Glass
JP
IPC
G06F 13/40
G06F 15/76
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