05581729 is referenced by 67 patents and cites 13 patents.

A multiprocessor computer system is provided having a multiplicity of sub-systems and a main memory coupled to a system controller. An interconnect module, interconnects the main memory and sub-systems in accordance with interconnect control signals received from the system controller. At least two of the sub-systems are data processors, each having a respective cache memory that stores multiple blocks of data and a respective master cache index. Each master cache index has a set of master cache tags (Etags), including one cache tag for each data block stored by the cache memory. Each data processor includes a master interface having master classes for sending memory transaction requests to the system controller. The system controller includes memory transaction request logic for processing each memory transaction request by a data processor. The system controller maintains a duplicate cache index having a set of duplicate cache tags (Dtags) for each data processor. Each data processor has a writeback buffer for storing the data block previously stored in a victimized cache line until its respective writeback transaction is completed and an Nth+1 Dtag for storing the cache state of a cache line associated with a read transaction which is executed prior to an associated writeback transaction of a read-writeback transaction pair. Accordingly, upon a cache miss, the interconnect may execute the read and writeback transactions in parallel relying on the writeback buffer or Nth+1 Dtag to accommodate any ordering of the transactions.

Title
Parallelized coherent read and writeback transaction processing system for use in a packet switched cache coherent multiprocessor system
Application Number
8/414763
Publication Number
5581729
Application Date
March 31, 1995
Publication Date
December 3, 1996
Inventor
Louis F Coffin III
San Jose
CA, US
Sue K Lee
San Mateo
CA, US
Paul Loewenstein
Palo Alto
CA, US
William C Van Loo
Palo Alto
CA, US
Zahir Ebrahim
Mountain View
CA, US
Satyanarayana Nishtala
Cupertino
CA, US
Agent
Test Albritton & Herbert Flehr Hohbach
Assignee
Sun Microsystems
CA, US
IPC
G06F 13/00
G06F 12/08
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