A plurality of integrated circuit chips (12) are packaged in a stack of chips in which a number of individual chip layers (10,120,130,132,134) are physically and electrically interconnected to one another and are peripherally sealed to one another to form an hermetically sealed package having a number of input/output pads (137a,139a,141a,156,158,160) on the surface of the upper (132) and lower (134) layers. Each chip layer comprises a chip carrier substrate having a chip cavity (22) on a bottom side and having a plurality of electrically conductive vias (40,42,44) extending completely around the chip cavity. Each substrate is formed with a peripheral sealing strip (46,48) on its top and bottom sides and mounts on its top side a chip that has its connecting pads (14) wire bonded to exposed traces (32,34) of a pattern of traces that are formed on the top side of the substrate and on intermediate layers (16,18,20) of this multi-layer substrate. The traces interconnect with the vias (40,42,44) that extend completely through the substrate, and each via is provided at the top and bottom sides of the substrate with a via connecting pad (40a41b), with the via pads on top and bottom sides all being arranged in identical patterns. Solder on the via pads and on the sealing strips is reflowed to effect a completely sealed package and to interconnect vias in each layer with vias in each other layer.