05577050 is referenced by 93 patents and cites 3 patents.

A logic circuit and a technique for repairing faulty memory cells internally by employing on-chip testing and repairing circuits in an ASIC system. The test circuit detects column line faults, row faults, and data retention faults in a memory array. The repair circuit redirects the original address locations of the faulty memory lines to the mapped address locations of the redundant column or row lines. This repair scheme includes redundant column lines attached to each of the I/O arrays in the memory array and redundant row lines to replace detected memory faults. These testing and repairing procedures are performed within the chip without the aid of any external equipment.

Title
Method and apparatus for configurable build-in self-repairing of ASIC memories design
Application Number
8/365286
Publication Number
5577050
Application Date
December 28, 1994
Publication Date
November 19, 1996
Inventor
Farzad Zarrinfar
Pleasanton
CA, US
Charles Li
San Jose
CA, US
Adam Kablanian
San Jose
CA, US
Owen S Bair
Saratoga
CA, US
Agent
Fenwick & West
Assignee
LSI Logic Corporation
CA, US
IPC
G01R 31/28
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