05574927 is referenced by 247 patents and cites 6 patents.

A RISC architecture computer configured for emulating the instruction set of a target computer to execute software written for the target computer, e.g., an Intel 80X86, a Motorola 680X0 or a MIPS R3000. The apparatus is integrated with a core RISC computer to form a RISC computer that executes an expanded RISC instruction. The expanded RISC instruction contains data fields which designate indirect registers that point to emulation registers that correspond to registers in the target computer. The width of the emulation registers is at least the width of those in the target computer. However, a field in the expanded RISC instruction restricts the emulated width to that required by a particular emulated instruction. Additionally, the expanded RISC instruction contains a field which designates the emulation mode for condition codes and selects logic to match the condition codes of the target computer. Target instructions are parsed and dispatched to sequences of one or more expanded RISC instructions to emulate each target instruction.

Title
RISC architecture computer configured for emulation of the instruction set of a target computer
Application Number
8/218225
Publication Number
5574927
Application Date
March 25, 1994
Publication Date
November 12, 1996
Inventor
Henry L Scantlin
Hermosa Beach
CA, US
Agent
Freilich Hornbaker Rosen
Assignee
International Meta Systems
CA, US
IPC
G06F 9/318
G06F 9/315
G06F 9/312
G06F 9/30
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