05560032 is referenced by 112 patents and cites 22 patents.

A high-performance, superscalar-based computer system with out-of-order instruction execution and concurrent results distribution for enhanced resource utilization and performance throughput. The computer system architecture includes an instruction fetch unit for fetching program instruction sets. Each instruction set includes a plurality of fixed length instructions with a prescribed program order (in-order). The architecture also includes an instruction execution unit for dynamically examining the instruction sets and scheduling instructions for execution, including out-of-order execution, among a plurality of functional units. The data results of the executed instructions are concurrently distributed to a temporary buffer and a register file array and managed by associated control logic, including a register renaming unit, a dependency checker unit, done control unit, and retirement control unit. The architecture also optimizes the scheduling of data paths in accordance with the type of computational function, including integer, floating point, and boolean.

Title
High-performance, superscalar-based computer system with out-of-order instruction execution and concurrent results distribution
Application Number
727058
Publication Number
5560032
Application Date
March 1, 1995
Publication Date
September 24, 1996
Inventor
Quang H Trang
San Jose
CA, US
Sze Shun Wang
San Diego
CA, US
Te Li Lau
Palo Alto
CA, US
Johannes Wang
Redwood City
CA, US
Yasuaki Hagiwara
Santa Clara
CA, US
Sanjiv Garg
Freemont
CA, US
Yoshiyuki Miyayama
Santa Clara
CA, US
Derek J Lentz
Los Gatos
CA, US
Le Trong Nguyen
Monte Sereno
CA, US
Agent
Sterne Kessler Goldstein & Fox P L L C
Assignee
Seiko Epson Corporation
JP
IPC
G06F 9/06
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