05559450 is referenced by 168 patents and cites 10 patents.

A field programmable gate array (FPGA) with a programmable function unit (PFU) that includes a look-up table (LUT) for implementing a plurality of functions including first and second RAM cells, and a programmable switching device dedicated to coupling and decoupling the RAM cells. The first and second RAM cells are coupled to respective first and second read/write ports. The RAM cells function individually as single-port RAM cells when decoupled by the switching device. However, the RAM cells share data to function collectively as a dual-port RAM cell when coupled by the switching device. The dual-port RAM cell is accessible by both the first and second read/write ports.

Title
Field programmable gate array with multi-port RAM
Application Number
8/507957
Publication Number
5559450
Application Date
July 27, 1995
Publication Date
September 24, 1996
Inventor
Satwant Singh
Macungie
PA, US
Kai Kit Ngai
Allentown
PA, US
Agent
James H Fox
Assignee
Lucent Technologies
NJ, US
IPC
H03K 19/177
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