05551005 is referenced by 55 patents and cites 4 patents.

In a computer system having a plurality of processors with internal caches, a method for handling race conditions arising when multiple processors simultaneously write to a particular cache line. Initially, a determination is made as to whether the cache line is in an exclusive, modified, invalid, or shared state. If the cache line is in either the exclusive or modified state, the cache line is written to and then set to the modified state. If the cache line is in the invalid state, a Bus-Read-Invalidate operation is performed. However, if the cache line is in the shared state and multiple processors initiate Bus-Write-Invalidate operations, the invalidation request belonging to the first processor is allowed to complete. Thereupon, the cache line is sent to the exclusive state, data is updated, and the cache line is set to the modified state. The second processor receives a second cache line, updates this second cache line, and sets the second cache line to the modified state.

Title
Apparatus and method of handling race conditions in mesi-based multiprocessor system with private caches
Application Number
8/201854
Publication Number
5551005
Application Date
February 25, 1994
Publication Date
August 27, 1996
Inventor
Matthew Fisch
Beaverton
OR, US
Wen Hann Wang
Portland
OR, US
Nitin V Sarangdhar
Beaverton
OR, US
Agent
Blakely Sokoloff Taylor & Zafman
Assignee
Intel Corporation
CA, US
IPC
G06F 12/08
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