05551001 is referenced by 68 patents and cites 16 patents.

A master-slave cache system has a large, set-associative master cache, and two smaller direct-mapped slave caches, a slave instruction cache for supplying instructions to an instruction pipeline of a processor, and a slave data cache for supplying data operands to an execution pipeline of the processor. The master cache and the slave caches are tightly coupled to each other. This tight coupling allows the master cache to perform most cache management operations for the slave caches, freeing the slave caches to supply a high bandwidth of instructions and operands to the processor's pipelines. The master cache contains tags that include valid bits for each slave, allowing the master cache to determine if a line is present and valid in either of the slave caches without interrupting the slave caches. The master cache performs all search operations required by external snooping, cache invalidation, cache data zeroing instructions, and store-to-instruction-stream detection. The master cache interrupts the slave caches only when the search reveals that a line is valid in a slave cache, the master cache causing the slave cache to invalidate the line. A store queue is shared between the master cache and the slave data cache. Store data is written from the store queue directly in to both the slave data cache and the master cache, eliminating the need for the slave data cache to write data through to the master cache. The master-slave cache system also eliminates the need for a second set of address tags for snooping and coherency operations. The master cache can be large and designed for a low miss rate, while the slave caches are designed for the high speed required by the processor's pipelines.

Title
Master-slave cache system for instruction and data cache memories
Application Number
8/267658
Publication Number
5551001
Application Date
June 29, 1994
Publication Date
August 27, 1996
Inventor
James S Blomgren
San Jose
CA, US
Jay C Pattin
Redwood City
CA, US
Russell W Tilleman
Palo Alto
CA, US
Earl T Cohen
Fremont
CA, US
Agent
Stuart T Auvinen
Assignee
Exponential Technology
CA, US
IPC
G06F 12/08
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