A data processing system includes a host processor and host memory means. The processor interacts with a plurality of peripheral units through an I/O system that includes a plurality of channels, one or more I/O processors (IOP's), and control data in a system area of the host memory means. Each channel has an associated busy bit in a vector, and is provided with a one position queue for dispatching work to the channel. Each queue has a bit in a vector indicating its full or empty status. A very efficient algorithm for the assignment of work for peripherals by the IOP's is provided in a system that provides for multiple paths through multiple channels between the host and a particular peripheral using the busy vector and queue vector.