05539690 is referenced by 167 patents and cites 23 patents.

Schemes for verifying the successful programming of a memory cell having more than two possible states are disclosed. Each program verify reference flash cell is set to have a V.sub.t that defines a boundary of a possible state for the selected flash cell. For a first embodiment, program verify reference flash cells are used in the place of read reference cells to perform a binary search read operation similar to a standard read operation for the memory device architecture. The data sensed by the write verify operation is compared to expected data. For a second embodiment, a single program verify reference flash cell is used to define a threshold voltage beyond which the floating gate of the selected flash cell must be programmed to pass the write verify operation. Thus, for the second embodiment, the program verify reference flash cell is used to verify the analog V.sub.t voltage level of the selected flash cell, rather than to determine the data of the selected flash cell, as is done for the first embodiment.

Title
Write verify schemes for flash memory with multilevel cells
Application Number
8/252747
Publication Number
5539690
Application Date
June 2, 1994
Publication Date
July 23, 1996
Inventor
Phillip M L Kwong
Folsom
CA, US
Kevin W Frary
Fair Oaks
CA, US
Mark E Bauer
Cameron Park
CA, US
Sanjay S Talreja
Folsom
CA, US
Agent
Blakely Sokoloff Taylor & Zafman
Assignee
Intel Corporation
CA, US
IPC
G11C 11/34
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