05535361 is referenced by 30 patents and cites 15 patents.

A cache controller for a multithreading multiprocessor system which starts an execution of another thread by suspending an ongoing execution of a thread when a cache miss happens. The cache controller comprises a cache directory unit for storing cache managing data including a footprint bit to indicate a mapping relation between at least one cache block in a main memory block, an access control unit for searching the directory unit based on an access requesting message inputted thereto through its input/output port connected to a processor to return one of a cache hit notice and a cache miss notice, as well as transferring messages with the main memory through its input/output port connected to a network, and a footprint bit changing device for setting the footprint bit in the cache managing data corresponding to a cache block at a cache hit, while resetting the footprint bit upon input of a positive responding message through the input/output port connected to the network to a fetch requesting message which has been sent therethrough at a cache miss.

Title
Cache block replacement scheme based on directory control bit set/reset and hit/miss basis in a multiheading multiprocessor environment
Application Number
8/66709
Publication Number
5535361
Application Date
May 24, 1993
Publication Date
July 9, 1996
Inventor
Kozo Kimura
Osaka
JP
Hiroaki Hirata
Kyoto
JP
Agent
Price Gess & Ubell
Assignee
Matsushita Electric Industrial
JP
IPC
G06F 12/08
View Original Source