05535340 is referenced by 71 patents and cites 4 patents.

A bus bridge situated between two buses includes two queues: an outbound request queue and an inbound request queue. Requests originating on the first bus which target a destination on the second bus are placed into the outbound request queue. Decoding circuitry within the bridge issues a deferred response if the request can be deferred. This deferred response is returned to the originating agent on the first bus, thereby informing the originating agent that the request will be serviced at a later time. Bus control circuitry coupled to the outbound request queue removes requests from the outbound request queue and executes them on the second bus. The bus control circuitry receives a response from the destination agent on the second bus in response to the execution of the outbound request. This response is returned to the originating agent either immediately or after passing through an inbound request queue. Both the outbound request queue and the inbound request queue have data buffers associated therewith for transferring data between the two buses. In addition, requests may originate on the second bus which target a device on the first bus (i.e., inbound requests). These inbound requests are placed in the inbound request queue and are executed on the first bus when removed from the inbound request queue.

Title
Method and apparatus for maintaining transaction ordering and supporting deferred replies in a bus bridge
Application Number
8/247026
Publication Number
5535340
Application Date
May 20, 1994
Publication Date
July 9, 1996
Inventor
Susan S Meredith
Hillsboro
OR, US
Mark A Gonzales
Portland
OR, US
D Michael Bell
Beaverton
OR, US
Agent
Blakely Sokoloff Taylor & Zafman
Assignee
Intel Corporation
CA, US
IPC
G06F 13/00
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