05532957 is referenced by 88 patents and cites 5 patents.

All of the components of a standard logic gate wherein high precision is required, preferably a NAND gate, are provided, preferably in bulk silicon and the remaining components required for a memory cell wherein relatively low precision is required, preferably an SRAM, as well as a mode select circuit are provided, preferably in a polysilicon layer over the bulk silicon. The mode select circuit is design to operate in plural modes, a two mode mode select circuit being the preferred embodiment. In any mode of operation as determined by the mode select circuit, all unused or unrequired circuitry is either isolated from the active portion of the circuit or used to enhance operation of required circuitry, such as, for example, operating in parallel therewith or in series therewith. The polysilicon layer, if used, can be disposed over the bulk silicon with vias and interconnects therebetween. The resulting circuit can require less circuit area required by a similar prior art circuits of both of the configurations obtainable, yet be capable of providing any one of plural selected functions. In addition, the improved hardware utilization is conducive to speed enhancement and lower power utilization due to paralleling.

Title
Field reconfigurable logic/memory array
Application Number
8/381180
Publication Number
5532957
Application Date
January 31, 1995
Publication Date
July 2, 1996
Inventor
Satwinder Malhi
Garland
TX, US
Agent
Richard L Donaldson
Jim Brady
Jacqueline J Garner
Assignee
Texas Instruments Incorporated
TX, US
IPC
G11C 11/00
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