05531022 is referenced by 212 patents and cites 7 patents.

The present invention is directed to a structure for packaging electronic devices, such as semiconductor chips, in a three dimensional structure which permits electrical signals to propagate both horizontally and vertically. The structure is formed from a plurality of assemblies. Each assembly is formed from a substrate having disposed on at least one surface a plurality of electronic devices. Each assembly is disposed in a stack of adjacent assemblies. Between adjacent assemblies there is an electrical interconnection means electrically interconnecting each assembly. The electrical interconnection means is formed from an elastomeric interposer. The elastomeric interposer is formed from an elastomeric material having a plurality of electrical conductors extending therethrough, either in a clustered or un-clustered arrangement. The electrical interconnection means is fabricated having a plurality of apertures extending therethrough. The array of apertures corresponds to the array of electronic devices on the substrates. The aperture and electrical interconnection means is disposed over the array of electronic devices so that the electrical interconnection means is between adjacent electronic devices. The stack of assemblies is compressed thereby compressing the electrical interconnection means between adjacent assemblies. The substrate or each assembly is formed from a thermally conductive material such as diamond. A heat dissipation means is thermally connected to the edges of the substrate to extract heat generated within the structure. Methods for fabricating the electrical interconnection means as a stand alone elastomeric sheet are described. The ends of the plurality of conductors in the electrical interconnection means are fabricated so that upon compression between adjacent assemblies there is a wiping action between the conductor ends and contact locations on the adjacent assemblies to form a good electrical contact therewith.

Title
Method of forming a three dimensional high performance interconnection package
Application Number
963346
Publication Number
5531022
Application Date
September 2, 1994
Publication Date
July 2, 1996
Inventor
George F Walker
New York
NY, US
Da Yuan Shih
Poughkeepsie
NY, US
Leathen Shi
Yorktown Heights
NY, US
John J Ritsko
Mt. Kisco
NY, US
Maurice H Norcott
Valley Cottage
NY, US
Paul A Lauro
Nanuet
NY, US
James L Hedrick Jr
Oakland
CA, US
Keith E Fogel
Bardonia
NY, US
Fuad E Doany
Katonah
NY, US
Brain S Beaman
Hyde Park
NY, US
Agent
Daniel P Morris
Assignee
International Business Machines Corporation
NY, US
IPC
H01R 9/09
H05K 3/40
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