05519854 is referenced by 53 patents and cites 2 patents.

A CPU core 4 can operate at either an internal clock frequency fclk or an external clock frequency mclk. When operating at the internal clock frequency fclk, write request signals are buffered in a write buffer 10. When operating at the external clock frequency mclk, write request signals are unbuffered. In order to avoid write request signals reaching a signal bus 6 out of order, an interlock is provided between the two paths so that any pending write request signals in the write buffer 10 will serve to hold off any write request signals that may issue through the other path. When a write request signal generated at the external clock frequency is blocked, this serves to stall the CPU core 4 since the blocked external clock write request signal may give rise to an externally generated abort which would alter subsequent processing.

Title
Write request interlock
Application Number
8/303325
Publication Number
5519854
Application Date
September 9, 1994
Publication Date
May 21, 1996
Inventor
Simon C Watt
Cambridge
GB
Agent
Albert C Smith
Assignee
Advanced RISC Machines
GB
IPC
G06F 1/12
G06F 7/00
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