05513327 is referenced by 166 patents and cites 59 patents.

A dynamic random access memory (DRAM). The DRAM comprises a first circuit for providing a clock signal and a conductor for coupling the DRAM to a bus. A receiver circuit is coupled to the conductor and the first circuit for latching information received from the conductor in response to detecting each of a rising edge of the clock signal and a falling edge of the clock signal. The receiver circuit may include a first input receiver for latching information in response to the rising edge of the clock signal and a second input receiver for latching information in response to the falling edge of the clock signal.

Title
Integrated circuit I/O using a high performance bus interface
Application Number
510898
Publication Number
5513327
Application Date
March 31, 1994
Publication Date
April 30, 1996
Inventor
Mark Horowitz
Palo Alto
CA, US
Michael Farmwald
Berkeley
CA, US
Agent
Blakely Sokoloff Taylor & Zafman
Assignee
Rambus
CA, US
IPC
G06F 13/00
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