05511029 is referenced by 48 patents and cites 5 patents.

In order to reduce a test time for a synchronous type memory device, a compression circuit compresses a plurality of memory cell data which are inputted in a plurality of read registers provided for a data output terminal to 1-bit data. A bank selection circuit selects an output of the compression circuit of either a bank #A or a bank #B. A tristate inverter buffer passes the 1-bit compression data selected by the bank selection circuit in accordance with a test mode command signal. The data output terminal outputs compressed data of a plurality of bits of memory cells. Thus, it is possible to simultaneously determine pass/fail of a plurality of memory cells, thereby reducing the test time.

Title
Test circuit in clock synchronous semiconductor memory device
Application Number
8/246582
Publication Number
5511029
Application Date
May 19, 1994
Publication Date
April 23, 1996
Inventor
Yasuhiro Konishi
Hyogo
JP
Seiji Sawada
Hyogo
JP
Agent
Lowe Price LeBlanc & Becker
Assignee
Mitsubishi Denki Kabushiki Kaisha
JP
IPC
G11C 7/00
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