05511024 is referenced by 79 patents and cites 21 patents.

As interfaces to DRAMs become more advanced and higher performance, the interfaces and signal lines required to support the interface become more expensive to implement. Therefore, it is desirable to minimize the number of signal lines and maximize the bandwidth of the signal lines interfacing to the DRAM in order to take advantage of the high performance of the signal lines in the interface. In the DRAM memory system of the present invention, the address and control lines and are combined and the information multiplexed such that the DRAM pins have roughly equal information rate at all times.

Title
Dynamic random access memory system
Application Number
71177
Publication Number
5511024
Application Date
February 25, 1994
Publication Date
April 23, 1996
Inventor
Michael P Farmwald
Portola Valley
CA, US
John G Atwood Jr
San Jose
CA, US
Billy W Garrett Jr
Mountain View
CA, US
Richard M Barth
Palo Alto
CA, US
John B Dillon
Palo Alto
CA, US
Frederick A Ware
Los Altos Hills
CA, US
Agent
Blakely Sokoloff Taylor & Zafman
Assignee
Rambus
CA, US
IPC
G06F 1/12
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