05506967 is referenced by 32 patents and cites 13 patents.

In a time-shared bus computer system with processors having cache memories, an adjustable invalidation queue for use in the cache memories. The invalidation queue has adjustable upper and lower limit positions that define when the queue is logically full and logically empty, respectively. The queue is flushed down to the lower limit when the contents of the queue attain the upper limit. During the queue flushing operation, WRITE requests on the bus are RETRYed. The computer maintenance system sets the upper and lower limits at system initialization time to optimize system performance under maximum bus traffic conditions.

Title
Storage queue with adjustable level thresholds for cache invalidation systems in cache oriented computer architectures
Application Number
8/78361
Publication Number
5506967
Application Date
June 15, 1993
Publication Date
April 9, 1996
Inventor
Bruce E Whittaker
Mission Viejo
CA, US
David M Kalish
Laguna Niguel
CA, US
Saul Barajas
Mission Viejo
CA, US
Agent
Robert R Axenfeld
Mark T Starr
Alfred W Kozak
Assignee
Unisys Corporation
PA, US
IPC
G06F 13/00
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