05497017 is referenced by 160 patents and cites 4 patents.

This invention is a DRAM array having stacked-capacitor cells of potentially 4F.sup.2 surface area (F being the photolithographic minimum feature width), and a 5-mask process for fabricating such an array. The array has a cross-point cell layout (i.e., a memory cell is located at each intersection of each digit line and each word line) and tungsten digit lines formed using a damascene process buried in the substrate. Each cell in the array has a vertical transistor, with the source/drain regions and channel region of the transistor being formed from epitaxially grown single crystal silicon. The stacked capacitor is fabricated on top of the vertical transistor.

Title
Dynamic random access memory array having a cross-point layout, tungsten digit lines buried in the substrate, and vertical access transistors
Application Number
8/378424
Publication Number
5497017
Application Date
January 26, 1995
Publication Date
March 5, 1996
Inventor
Fernando Gonzales
Boise
ID, US
Agent
Holland & Hart
Agent
Angus C Fox III
Assignee
Micron Technology
ID, US
IPC
H01L 29/76
H01L 27/108
View Original Source