05493684 is referenced by 130 patents and cites 11 patents.

An integrated processor is provided that includes a CPU core coupled to a variety of on-chip peripheral devices such as a DMA controller, an interrupt controller, and a timer. The integrated processor further includes a power management message unit coupled to the DMA controller, interrupt controller, and timer for monitoring the internal interrupt and bus request signals of the integrated processor. The power management message unit may also monitor other selected activities of the integrated processor such as activities of a floating-point coprocessing subunit. Based on the detected activities, if any, the power management message unit encodes a message on a power management message bus to thereby provide information regarding the internal events of the integrated processor to an external power management unit. Power management decisions are made by an external power management unit. The power management unit receives the encoded messages on the power management message bus and responsively makes decisions as to the appropriate power management mode to enter. The power management unit includes a clock control unit coupled to an internal clock generator of the integrated processor for controlling the frequencies of a CPU clock signal and a system clock signal. The power management unit further includes a power control unit for controlling the application of power to various external peripheral devices.

Title
Power management architecture including a power management messaging bus for conveying an encoded activity signal for optimal flexibility
Application Number
8/223984
Publication Number
5493684
Application Date
April 6, 1994
Publication Date
February 20, 1996
Inventor
Rita M O Brien
Austin
TX, US
James R MacDonald
Buda
TX, US
Douglas D Gephardt
Austin
TX, US
Agent
B Noel Kivlin
Assignee
Advanced Micro Devices
CA, US
IPC
G06F 1/32
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