A data processor has a plurality of execution units (12), a rename buffer (14) coupled to at least one of the execution units and a plurality of architectural registers (16) coupled to at least one execution unit and to the rename buffer. The rename buffer periodically receives and stores the result and periodically receives requests for the operand. Each received result and operand is associated with an architectural register. The rename buffer periodically forwards one of a set of received results to an execution unit. Each received result of the set is associated with the same architectural register. The rename buffer is operable to determine which entry is the most recently allocated among several that will update the same architectural register. This ability to both manage results destined for the same architectural register and to forward only the appropriate value increases data processor throughput and reduces instruction stalls.