A digital circuit design assist system is directed to provide a system which independently verifies hardware divided into a plurality of units or the hardware and software, and reduces the design time. The system includes a functional model storage unit 1 for storing functional models in order to design hardware for a desired digital circuit including the hardware alone or the hardware and firmware, and functionally expressing the digital circuit by a hardware description language through a text editor 15 by coding input. Logic synthesis system 2 is provided for converting the functional model to a structural model, structurally expressed by the hardware description language. Structural model storage unit 3 is provided for storing the structural model, and a language model library storage unit 4 is provided for storing language models each expressing each of a plurality of components constituting the hardware by the hardware description language. Hardware description language simulation system 5 is provided for verifying correctness of the logic of the hardware from the functional model, the structural model and the language model.