05491790 is referenced by 6 patents and cites 13 patents.

A processing unit couples to a system bus in common with a peer processor, a main memory, in addition to other units, and includes a microprocessor which tightly couples to a local memory also accessible from such bus. The processing unit also includes an addressable electrically erasable programmable read only memory (EEPROM) unit which is coupled to the microprocessor and the system bus. The EEPROM unit stores in first and second separate regions, both of which occupy the same address space normally allocated for storing the microprocessor's boot code, on-board diagnostic (OBD) routines and operating system boot routines, respectively. EEPROM control circuits at power-up, condition the EEPROM unit to address the first region for executing OBD routines to verify that the processing unit is operating properly, including the ability to properly issue commands to units connected to the system bus. Following loading of the peer processor operating system, the EEPROM control circuits, in response to commands from the system bus, enable the microprocessor to address the second region for executing boot routines for loading its operating system.

Title
Power-on sequencing apparatus for initializing and testing a system processing unit
Application Number
775864
Publication Number
5491790
Application Date
April 22, 1994
Publication Date
February 13, 1996
Inventor
Thomas S Hirsch
Bedford
MA, US
Keith L Petry
North Reading
MA, US
Chester M Nibby Jr
Beverly
MA, US
Richard A Lemay
Carlisle
MA, US
James W Keeley
Nashua
NH, US
Agent
John S Solakian
Faith F Driscoll
Assignee
Bull HN Information Systems
MA, US
IPC
G06F 9/445
View Original Source