05491703 is referenced by 142 patents and cites 11 patents.

A method of accessing a content addressable memory having a plurality of RAM cells connected in an array of rows and columns, each row having a plurality of cells for storing a data word, at least one additional cell for storing a checking bit and a match line for providing a signal to indicate when a match occurs between an input data word and data stored in a row of cells, which method comprises storing in at least one row of cells a data word in data cells of the row and a checking bit in said at least one additonal cell of the row, the checking bit having a value dependent on the content of the data word in accordance with an error checking system, and controlling a memory accessing system to effect an associate operation by inputting to the columns of cells an input word with an input checking bit dependent on said input word in accordance with the same error checking system, comparing the input word and input checking bit with stored contents of each row of cells and in any row where a mismatch of the input data word with the stored data word occurs causing at least two cells in that row to change a signal level on a match line for that row, said memory accessing system being arranged to operate with a time delay for each associate operation which is less than that required for a single cell mismatch. The invention also provides a content addressable memory.

Cam with additional row cells connected to match line
Application Number
Publication Number
Application Date
June 29, 1993
Publication Date
February 13, 1996
Anthony I Stansfield
Richard J Gammack
St. James
Catherine L Barnaby
Coalpit Heath
Felsman Bradley Gunter & Dillon
SGS Thomson Microelectronics
H03M 13/00
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