05487156 is referenced by 177 patents and cites 8 patents.

A processor architecture is described which operates with improved computational efficiency using instruction fetching functions that are decoupled from instruction execution functions by a dynamic register file. The instruction fetching function operates in free-running mode which does not stop if a fetched instruction cannot be executed due to data being unavailable or due to other instruction dependencies. Branch instructions are taken in a predicted direction and the results of execution of all instructions are provisionally stored pending validation or invalidation on the basis of the dependencies becoming available later. For branches of executed instructions that are later invalidated, the results of the executed instructions are flushed from provisional storage and the initial instruction which previously executed at the beginning of a branch on predicted dependencies is re-executed on the actual data that subsequently became available, and all subsequent instructions in such branch are also re-executed on the basis of dependencies actually available from execution of previous instructions in such branch.

Title
Processor architecture having independently fetching issuing and updating operations of instructions which are sequentially assigned and stored in order fetched
Application Number
451403
Publication Number
5487156
Application Date
December 5, 1990
Publication Date
January 23, 1996
Inventor
Bruce D Lightner
10305 Moselle St., San Diego, 92131
CA, US
John E Spracklen
3540 Moultrie Ave., San Diego, 92117
CA, US
Gary A Gibson
2624 La Golandrina, Carlsbad, 92009
CA, US
Merle A Schultz
1013 Fern St., Escondido, 92027
CA, US
Valeri Popescu
12686 Monterey Cypress, San Diego, 92130
CA, US
Agent
Townsend and Townsend and Crew
IPC
G06F 9/30
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