05487044 is referenced by 18 patents and cites 5 patents.

A semiconductor memory device having memory cells arranged in a matrix, each of the memory cells having input/output terminals, word lines for selecting the memory cells, pairs of bit lines connected to the input/output terminals, bit line pulling-up means for pulling up the potential of the bit lines, bit line loading means connected to another pair of bit lines and bit line equalizing means provided for the bit lines for equalizing the potential of the bit lines by allowing conduction between the bit lines before data is read from a selected memory cell.

Title
Semiconductor memory device having bit line equalizing means
Application Number
34417
Publication Number
5487044
Application Date
January 17, 1995
Publication Date
January 23, 1996
Inventor
Kouji Nakao
Yokohama
JP
Yasumitsu Nozawa
Yokohama
JP
Shigeto Mizukami
Kawasaki
JP
Takayuki Kawaguchi
Yokohama
JP
Agent
Foley & Lardner
Assignee
Kabushiki Kaisha Toshiba
JP
IPC
G11C 7/00
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