05485576 is referenced by 45 patents and cites 12 patents.

A fault tolerant system management bus architecture for a networking chassis includes a primary path for transmission of system management information and a secondary path for transmission of system management information in the event of failure of the primary path. The primary path includes a first microprocessor controller, coupled between the first system management bus and the processor located on a networking module. The secondary path for transmission of system management information includes a second microprocessor controller system and a dual-port memory. The second microprocessor control system is coupled to the second system management bus and to the dual-port memory. The dual-port memory is also coupled to the processor located on the networking module. The dual-port memory provides the interface between the CPU in the networking module and the second microprocessor control system, thus providing isolation and allowing the memory to be accessible by either processor. Environmental information and module identification information are stored in the dual-port memory. In the event of failure of the primary transmission path, the environmental information and module identification information can be accessed and transmitted over the backup transmission path.

Title
Chassis fault tolerant system management bus architecture for a networking
Application Number
8/188033
Publication Number
5485576
Application Date
January 28, 1994
Publication Date
January 16, 1996
Inventor
Chris Oliver
10 Stanley's Pond Dr., Rochester, 03869-4954
NH, US
Brendan Fee
34 Pemberton Rd., Nashua, 03036
NH, US
Agent
Wolf Greenfield & Sacks
IPC
H04L 12/40
H04L 29/14
G06F 11/20
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