05485422 is referenced by 116 patents and cites 14 patents.

A memory device is disclosed which includes memory cells having m possible states, where m is at least 2. The memory device includes a multiplexed pair of output paths, wherein each output path is coupled to sense the state of a memory cell and includes a read path circuit, a column load circuit, and a comparator. Provided between the pair of output paths is a switching circuit for coupling the comparators to one another in response to a control signal. For single-bit read operations, each output path senses and outputs the data of the associated memory cell, and the control signal is inactive. When the control signal is active, the read path circuit and column load circuit of one of the output paths is disabled and the switching circuit couples the other read path circuit to the second comparator such that the state of the memory cell is sensed by two comparators.

Title
Drain bias multiplexing for multiple bit flash cell
Application Number
8/252684
Publication Number
5485422
Application Date
June 2, 1994
Publication Date
January 16, 1996
Inventor
Sanjay S Talreja
Folsom
CA, US
Kevin W Frary
Fair Oaks
CA, US
Mark E Bauer
Cameron Park
CA, US
Agent
Blakely Sokoloff Taylor & Zafman
Assignee
Intel Corporation
CA, US
IPC
G11C 11/34
View Original Source