05482881 is referenced by 18 patents and cites 5 patents.

A flash EEPROM having reduced column leakage current suitably includes cells with more uniform erase times arranged in an array. An intermediate n+ implant immediately following the DDI implant step suitably provides an enhanced doping profile in the tunneling region, which increases the rate at which F-N tunneling occurs to erase the cells, and which increases the uniformity of F-N tunneling rates among memory cells within the array. A thermal cycle drives the intermediate n+ implant deeper into the tunneling region. Alternatively, an n+ implant may be performed at a relatively large angle with respect to the semiconductor substrate, which improves the doping concentration in the tunneling region of the source.

Title
Method of making flash EEPROM memory with reduced column leakage current
Application Number
8/403460
Publication Number
5482881
Application Date
March 14, 1995
Publication Date
January 9, 1996
Inventor
Salvatore F Cagnina
Los Altos
CA, US
Scott Luning
Menlo Park
CA, US
Yuan Tang
San Jose
CA, US
Jian Chen
San Jose
CA, US
Agent
Michael A Lechter
Assignee
Advanced Micro Devices
CA, US
IPC
H01L 21/8247
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