05481563 is referenced by 50 patents and cites 7 patents.

A jitter measurement system for a serial digital data link includes a clock recovery element effective to separate a clock signal from the digital data bits being transmitted. The clock signal is applied first to a programmable delay element whose output is applied to as a first input to a decision circuit. The second input to the decision is the serial data stream. The relation of the data to the clock is initially set so that the clock is sampling the data at approximately the transition point of the data. Depending on the exact location of the data relative to the clock signal, the result of the sampling process will yield one of two results. First, if the data transition occurs before the clock transition, no error results. However, if the clock transition occurs before the data transition, an error results. An error ratio detector circuit determines an error ratio which is compared to a predetermined reference. If the reference is exceeded by error ratio, the delay of the programmable delay circuit is adjusted in a closed loop fashion to make the error ratio correspond to the predetermined allowable error rate.

Jitter measurement using a statistically locked loop
Application Number
Publication Number
Application Date
March 14, 1994
Publication Date
January 2, 1996
John D Hamre
Haugen and Nikolai
Network Systems Corporation
H04B 3/46
H04L 7/00
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