05471430 is referenced by 53 patents and cites 6 patents.

A synchronous semiconductor memory device includes an automatic refresh detection circuit for detecting that an automatic refresh mode is specified in accordance with an automatic refresh command, an address counter for generating a refresh address, a refresh execution unit for refreshing a memory array in accordance with an automatic refresh detection signal and the refresh address, an inactivation circuit for inactivating the refresh execution unit after a lapse of a prescribed time in accordance with the automatic refresh detection signal, a counter check mode detection circuit for bringing the inactivation circuit into an inoperable state in accordance with a counter check mode command, and a second inactivation circuit for inactivating the refresh execution unit in accordance with a precharge detection signal generated in response to a precharge command. Thus synchronous semiconductor memory device with an operation mode which can test the function of an internal refresh address counter is provided.

Title
Test circuit for refresh counter of clock synchronous type semiconductor memory device
Application Number
8/245784
Publication Number
5471430
Application Date
May 19, 1994
Publication Date
November 28, 1995
Inventor
Yasuhiro Konishi
Hyogo
JP
Seiji Sawada
Hyogo
JP
Agent
Lowe Price LeBlanc & Becker
Assignee
Mitsubishi Denki Kabushiki Kaisha
JP
IPC
G11C 11/34
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