05471152 is referenced by 19 patents and cites 4 patents.

A storage element for testing delay paths in integrated circuits is described. The storage element may be used in integrated circuits having matrices of probe and sense lines. The storage element generates a logic transition on an input to a delay path, the logic transition being closely synchronized with a clock signal. The storage element comprises a data input and a data output coupled to the input to the delay path. A master latch receives data from the data input through a first switch, the first switch being controlled by the complement of the clock signal. A slave latch receives data from the master latch through a second switch, the second switch being controlled by the true of the clock signal. A first sense input loads a first logic state into the master latch through a third switch, the first sense input being coupled to one of the IC's sense lines. The third switch is controlled by one of the IC's probe lines. A second sense input loads a second logic state into the slave latch through a fourth switch, the second sense input being coupled to another one of the IC's sense lines. The fourth switch is controlled by a second control signal. The second logic state replaces the first logic state in the slave latch upon application of the clock signal. The desired signal transition is generated where the first logic state is different from the second logic state.

Title
Storage element for delay testing
Application Number
8/133588
Publication Number
5471152
Application Date
October 8, 1993
Publication Date
November 28, 1995
Inventor
Prab Varma
Mountain View
CA, US
Rustam Mehta
Sunnyvale
CA, US
Tushar Gheewala
Los Altos
CA, US
Agent
Townsend and Townsend and Crew
Assignee
CrossCheck Technology
CA, US
IPC
G01R 31/02
G01R 31/00
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