A memory system contains a plurality of memory cells, a sensing circuit, and a translator circuit. The memory cells store one of a plurality of threshold levels, wherein the threshold levels demarcate windows for designating more than a single bit of data for each memory cell. The sensing circuit, coupled to the memory cells, generates at least one binary coded bit from the threshold level sensed. A translator circuit translates the binary coded bits to gray coded bits such that only one bit changes state between adjacent threshold levels. Because of this, a decrease from one threshold level to a lower adjacent threshold level in a memory cell results in the change of only a single bit of data, thus improving the memory system reliability. The memory system also includes the ability to store threshold states in either a multi-level cell mode or a standard level cell mode. In the standard cell mode, the translator circuit directly passes the binary coded bits without performing any translation.