05440752 is referenced by 84 patents and cites 10 patents.

A computer system comprising a microprocessor architecture capable of supporting multiple processors. Data transfers between data and instruction caches, I/O devices, and a memory am handled using a switch network. Access to memory buses is controlled by arbitration circuits which utilize fixed and dynamic priority schemes. A test and set bypass circuit is provided for preventing a loss of memory bandwidth due to spin-locking. A row match comparison circuit is provided for reducing memory latency by giving an increased priority to successive requests for access to memory locations having the same row address. Dynamic switch/port arbitration is provided by changing device priority based on the intrinsic priority of the device, the number of times that a request has been serviced based on a row match, the number of times that a device has been denied service, and the number of times that a device has been serviced.

Title
Microprocessor architecture with a switch network for data transfer between cache, memory port, and IOU
Application Number
7/726893
Publication Number
5440752
Application Date
July 8, 1991
Publication Date
August 8, 1995
Inventor
Le Trong Nguyen
Monte Sereno
CA, US
Cheng Long Tang
San Jose
CA, US
Te Li Lau
Palo Alto
CA, US
Yasuaki Hagiwara
Santa Clara
CA, US
Derek J Lentz
Los Gatos
CA, US
Agent
Sterne Kessler Goldstein & Fox
Assignee
Seiko Epson Corporation
JP
IPC
G06F 13/40
G06F 13/38
G06F 13/00
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