05434745 is referenced by 178 patents and cites 15 patents.

Disclosed is a stacked die carrier assembly and method for packaging and interconnecting silicon chips such as memory chips. The carrier is constructed from a metalized substrate onto which the chip is attached. The chip is wire bonded to the conductor pattern on the substrate. Each conductor then is routed to the edge of the substrate where it is connected to a half-circle of a metalized through hole. A frame is attached on top of this substrate. This frame has also a pattern of half-circle metalized through holes that aligns with the holes on the bottom substrate. The combination of the bottom substrate with the silicon die, and the frame on top, forms a basic stackable unit. Several such units can be stacked and attached on top of each other. The top unit can finally be covered with a ceramic lid that also has a matching half-circle metalized through hole pattern along its edge. To electrically interconnect the stacked assembly conductive epoxy can be applied in the grooves formed by the aligned half-circle plated through holes.

Title
Stacked silicon die carrier assembly
Application Number
8/280315
Publication Number
5434745
Application Date
July 26, 1994
Publication Date
July 18, 1995
Inventor
Bjarne Heggli
Phoenix
AZ, US
Leonard Reeves
Phoenix
AZ, US
Hamid Shokrgozar
Phoenix
AZ, US
Agent
Joseph W Mott
Assignee
White Microelectronics Div of Bowmar Instrument
AZ, US
IPC
H01L 21/18
H05K 7/00
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