05428761 is referenced by 224 patents and cites 13 patents.

A computer system provides transactional memory operations, in which a selected data item in a shared memory is referenced by a CPU in local storage (such as a write-back cache). The CPU performs some operation to alter or use the data item while it is in local memory, and meanwhile monitors the bus to the shared memory to see if another processor references the selected location (as by a snoop mechanism); if so, a status bit is toggled to indicate that the transaction must be scrubbed. When the operation has been completed by the CPU, it attempts to "commit" the transaction, and this includes checking the status bit; if the bit has been toggled, the transaction aborts, the data item is invalidated in local memory, and the selected location in shared memory is not affected. If the status bit has not been toggled, the transaction is committed and the altered data item becomes visible to the other processors, and may be written back to the shared memory. To distinguish these transactional memory operations from standard loads and stores to memory, an indication of "transactional" or "not transactional" is added to the local storage, i.e., to a cache line. The transactional memory operations have the characteristics of serializability and atomicity.

Title
System for achieving atomic non-sequential multi-word operations in shared memory
Application Number
7/849887
Publication Number
5428761
Application Date
March 12, 1992
Publication Date
June 27, 1995
Inventor
J Eliot B Moss
Amherst
MA, US
Maurice Herlihy
Brookline
MA, US
Agent
Denis G Maloney
Arthur W Fisher
Assignee
Digital Equipment Corporation
MA, US
IPC
G06F 12/00
View Original Source