05426072 is referenced by 238 patents and cites 11 patents.

A method of providing a first and a second Silicon-on-Insulator (SOI) wafer, wherein each SOI wafer includes a silicon layer separated from a bulk silicon substrate by a layer of dielectric material, typically SiO2. Next, at least one electrical feedthrough is formed in each of the silicon layers and active and passive devices are formed in each of the thin silicon layers. Next, interconnects are formed that overlie the silicon layer and are electrically coupled to the feedthrough. One of the wafers is then attached to a temporary substrate such that the interconnects are interposed between the thin silicon layer and the temporary substrate. The bulk silicon substrate of the wafer having the temporary substrate is then etched to expose the dielectric layer. Further interconnects are then formed through the exposed dielectric layer for electrically contacting the at least one feedthrough. This results in the formation of a first circuit assembly. A next step then couples the further interconnects of the circuit assembly to the interconnects of the second SOI wafer, the second SOI wafer having a bulk substrate, a dielectric layer overlying a surface of the substrate, and a layer of processed silicon overlying the dielectric layer. The temporary substrate is then removed. Additional circuit assemblies may then be stacked and interconnected to form a 3d integrated circuit.

Title
Process of manufacturing a three dimensional integrated circuit from stacked SOI wafers using a temporary silicon substrate
Application Number
8/6601
Publication Number
5426072
Application Date
January 21, 1993
Publication Date
June 20, 1995
Inventor
Ronald M Finnila
Carlsbad
CA, US
Agent
W K Denson Low
W C Schubert
Assignee
Hughes Aircraft Company
CA, US
IPC
H01L 21/60
H01L 21/58
H01L 21/56
H01L 21/283
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